Computer Sciences and Information Technology
Title : | An Energy Efficient IoT Processor built using an Optimized Near-Threshold Voltage Standard Cell Library |
Area of research : | Computer Sciences and Information Technology, Engineering Sciences |
Focus area : | Internet of Things |
Principal Investigator : | Dr Anand Bulusu, Assistant Professor, Indian Institute of Technology (IIT) Roorkee |
Timeline Start Year : | 2019 |
Contact info : | anand.bulusu@ece.iitr.ac.in ; bishnu.das@ece.iitr.ac.in ; sudeb.dasgupta@ece.iitr.ac.in |
Details
Executive Summary : | Background: Lowering the supply voltage Vdd from the super-threshold regime to the sub/near-threshold (NTV) regime is now being explored actively for applications, such as hand-held/portable devices, medical devices and remotely located wireless sensor networks, where high performance is not a major consideration. The main challenges in NTV designs are: (a) A weak current flow resulting in speed degradation. (b) The device current is exponentially dependent on the transistor threshold voltage Vth, temperature T and Vdd. Hence, process temperature and voltage (PVT) variations can result in malfunctioning and reduction in yield of NTV circuits.
Approach: In designing a sub/near threshold library, Investigators would follow a three-pronged approach:
One, using more transistors and aiding circuits to improve the variation reliability of critical cells such as Flip-Flops/latches.
Two, developing circuit performance models of the sources of variations, especially those which are systematic in nature. These models can then be considered in circuit design methodologies (for optimizing transistors sizes and layout). In addition, these models can be used to estimate the statistical variation of cell performance due to PVT variations (including random variations). They would develop this two-pronged design strategy and design the sub/near threshold standard cell library proposed in this project.
Three, SEU and radiation tolerance of sequential elements of an NTV library would be addressed. For this, on one hand radiation hardened by design (RHBD) sequential circuits using redundant transistors and layout techniques would be developed. On the other hand, a critical charge model, developed recently by the group, would be used to size/layout transistors and also estimate the impact of PVT variations. There are serious challenges in NTV standard cell characterization techniques too: These challenges are due to the large nonlinear variations in the output currents and input/output capacitances of logic gates with terminal voltages and PVT parameters. They would develop new characterization methods, which would be adaptations of the ECSM/CCS methods, for the NTV standard cell library, based on investigator’s earlier work. To validate the 28 nm NTV standard cell library, they would synthesize an NTV 8085 using it. To create new and useful Indian IPs in the SCL 180 nm CMOS technology, they would design an IoT sensor edge processor with a small instruction set. |
Co-PI: | Dr Bishnu Prasad Das, Associate Professor, Dr Sudeb Dasgupta, Head of Department, Indian Institute of Technology (IIT) Roorkee, Dr Gaurav Trivedi, Associate Professor, Indian Institute of Technology (IIT) Guwahati |
Total Budget (INR): | 48,95,000 |
Achievements : | • In the near-threshold regime, a design methodology is proposed to optimize the data-path performance
• In the sub/near-threshold regime, an energy-efficient resilient circuit design technique is proposed.
• Investigators have designed a standard cell library for Combinational and Sequential circuits. |
Organizations involved