Executive Summary : | The continuous scaling of CMOS process is favoured by digital design. However, analog designs using conventional voltage domain processing become more challenging in these scaled processes. The only apparent benefit of these scaled process for analog design is the higher operating speeds. Hence processing analog signal in time domain is a way to go to take benefit of process scaling. There are several realization of ADC using time domain processing. However, one common major factor limiting the performance of these ADCs is the linearity performance of voltage to time converter (VTC) or voltage to frequency converter (VCO). The linearity performance of VTC degrades at higher operating frequencies. This results in higher total harmonic distortion (THD) at these higher operating frequencies. Hence processing a signal with large swing at higher frequency degrades the overall performance. This leads us to conclude that large swing signal should be processed only at a relatively lower frequencies or only a small swing signal should be processed at a higher frequencies. Thus one way to relax the linearity requirement on VTC is to operate it at a lower frequency. This can become possible if we realize the VTC in a time interleaved fashion. But as we know that time interleaving architecture may introduce interleaving artefacts and can thus limit the overall performance of the ADC. This can be avoided by using two step conversion architecture for realizing ADCs where time interleaving is realized only in first stage, while the second stage which process a small swing residue signal operates at full rate. The interleaving artefacts caused by VTC are captured by coarse ADC as well as residue signal processed by fine ADC. Thus it is possible to cancel the effect of these artefacts. The residue signal which is processed by fine conversion stage has a relatively lower swing and hence fine conversion stage can operate at a relatively higher frequency. Thus the proposed architecture helps in realizing a time domain ADC with an improved linearity. No interstage gain is proposed to be used in this architecture because the performance of medium resolution and wide bandwidth time domain ADCs are currently limited by nonlinearity and not the thermal noise. The proposed idea will be designed using CMOS process in advanced nodes such as 40nm and the design will be fabricated on silicon chip through CMOS foundries. The fabricated chip will then be validated in our testing lab and the measured performance will be verified. The results obtain through this project will help in realizing a wide bandwidth time domain ADC with an improved linearity. The theoretical analysis carried out during execution of this project will help in developing a better understanding of the behaviour of voltage to time converter in particular or time domain ADCs in general. |