Executive Summary : | Advent of cheap electronics, cloud, IoT, portable devices, mobile platforms, digitization of information, smart-cities etc, has led to generation of enormous amounts of data. Characteristics central to this big-data are its asynchronous and non-standardized nature. Vast amount of data by itself is of less value, however the ability to efficiently process this data leading to meaningful insights is valuable. Data processing techniques such as- pattern extraction, recognition, classification etc. are relevant in this context. Conventional Von Neumann computing hardware is inefficient (latency, power/energy) for implementing massive data processing tasks. Similar to most scientific fields, inspiration form nature; in particular functioning of the mammalian brain provides valuable insights for complex data processing. The mammalian brain is known to compute in a non-Von Neumann way where memory and processing are not isolated tasks and the memory is intelligent. Plasticity, re-configurability, dense connectivity, and inherent redundancy in the elements of mammalian brain (neurons, synapses etc.) make it an extremely efficient, low-power, unsupervised computing engine. Through this project we wish to exploit bio-inspired concepts for design and demonstration of dedicated neuromorphic and memory-centric computing hardware. The project is an ambitious inter-disciplinary effort involving knowledge from the fields of computational neuroscience, nano electronic devices/circuit-design and computer architecture. In Phase-1, we will investigate neuromorphic and memory inspired learning rules compatible for implementation on nanoelectronic CMOS-NVM hardware. Algorithms of interest may include: synaptic-plasticity based learning mechanisms such as long-term/short-term plasticity (LTP/STP), Spike-Time Dependent Plasticity (STDP) and memory intensive computing. In Phase-2, novel circuit-device architectures will be designed, fabricated and characterized. In final Phase-3, the novel architectures will be interfaced with real-world sensors for PoC demonstration. For architectural simulation study in Phase-1 and 2, we will utilize and upgrade our indigenously built platform: ‘MASTISK'. Circuit-device exploration will be performed using CAD tools. Fabrication of CMOS components will be done at professional semiconductor foundry, while PoC nanodevices will be fabricated in university cleanroom. Phase-3 PoC demo involving full system (circuit, device, architecture, and algorithm) will be achieved with the help of advanced and custom semiconductor test-bench. Real-world computing application will be demonstrated by integrating the setup with off-the-shelf sensor. End-users of the proposed research can be from fields of: defence, consumer electronics, bio-medical prosthetic, edge-computing, artificial intelligence, and energy efficient data-analytics. Phase-1, 2 focus on novel research, while Phase-3 focuses on PoC related engineering challenges. |