Research

Computer Sciences and Information Technology

Title :

Incorporating cab-signalling into interlocked signalling design with verification

Area of research :

Computer Sciences and Information Technology

Focus area :

Tools for signal interlocking

Principal Investigator :

Dr. Chittaranjan Mandal, Indian Institute Of Technology Kharagpur, West Bengal

Timeline Start Year :

2019

Timeline End Year :

2022

Contact info :

Details

Executive Summary :

The objective of this project is to create tools for signal interlocking and enable trains to run at high speeds under adverse conditions, such as foggy conditions. This is a problem faced by the railways and is, therefore, a problem that needs to be satisfactorily addressed. The impact of this technology will be better operation of trains under Indian conditions. The strength of the proposal is that it rests on the experience of developing signal interlocking tools as a proof of concept for South Eastern Railways. This project aims to extend that work and also develop techniques for running trains at high speed under adverse weather conditions. This aspect was not part of the work done earlier. Wireless location determination using a standard wireless communication protocol (GSM-R/LTE/other) and development of algorithms and protocols for exchanging data for location determination and dissemination are tasks identified for cab. As zonal variations exist in the schemes for application logic generation and also RCC generation, techniques will be developed for rule based generation of RCCs and application logic. Verification techniques developed to verify safety aspects of the application logic with respect to the RCC will have to be extended to cover the newer aspects of operation.

Total Budget (INR):

60,41,200

Achievements :

1. Route conflicts enumeration: Layout editor provides a novel approach for automatically detecting conflicts between routes by considering various interlocking rules of the Indian Railway. The primary source of conflict between routes is that they have some common track circuits.

Organizations involved