Executive Summary : | Ferroelectric FETs (FeFETs) are polarization-induced devices that can be used to realize non-volatile memory (NVM) and potentially multi-bit memory, which are important features in conventional memory and compute-in-memory (CIM) based artificial intelligence (AI) hardware accelerators. The existing SRAM-based CIM is an emerging approach to resolve the bottleneck of conventional digital accelerators, but it consumes a large area, has read stability issues, is highly prone to variations/noise, and is not energy efficient. FeFET memory is a potential replacement for SRAM in analog CIM due to its multiple polarization loops and retention of its polarization state. However, challenges in FeFET include device variations and memory window collapse. The main objectives of the project include creating an 1T-1C FeFET memory array with 2-bit precision (4-valued) memory cell for use in NVM and CIM, an analog CIM array with 2-bit precision weights and MAC operation on the bitline, a word line driver circuit ensuring a reliable write scheme for the FeFET memory array, a circuit/layout design methodology ensuring analog MAC operation for multi-bit memory, and a methodology to optimize the FeFET gate stack while considering variability. A TCAD simulation setup with a ferroelectric gate stack will be created, calibrated with experimental data from IPMS, Germany, and following the device structure and doping profiles in the TCAD setup. The technical outcome of the project will provide a fundamental understanding of the physical origin of memory window in FeFETs and its variability, as well as CIM/NVM design with multi-bit storage using FeFETs. |