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Research Agricultural
Total number of Record(s): 21502
Title | Principal Investigator | Start Year | Funding Agency | Focus Area |
---|---|---|---|---|
Multi-wavelength LIDAR for terrain mapping and atmospheric measurement | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Electro-optical sensors | ||
Processing software tool for NavIC receiver/receiver network | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Navigation Tools | ||
Survey and analysis of different types of SOTM system and simulation of their tracking and control algorithms and implementation | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Satellite communication, antenna and control system for antenna tracking | ||
Multiphysics modeling and simulation of MEMS based electro spray thruster | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Micro-fluidics | ||
Drive, readout and control electronics for capacitive MEMS gyroscope | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Sensor Circuits and Signal Processing | ||
Design of SAR ADC 14/16 bit 20/10 Mbps | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | VLSI Design | ||
Modeling of high voltage (10-20, 40-60V) N /P LDMOS devices developed at SCL in 180nm CMOS baseline process technology | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Semiconductor Device Modeling | ||
Modeling of devices (SPICE based) (in partially depleted SOI-CMOS process and PDSOI analog cell library considering floating-body effect (FB) and self-heating effect | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | Partially Depleted SOI-CMOS process development in 180nm | ||
Design of PLL with VCO, 40MHz -1000MHz, Ultra low phase noise -110dBc/Hz, very low RMS jitter<180fs | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | VLSI Design | ||
Design of SAR ADC 14/16 bit 20/10 Mbps | Department of Space (DOS) and Indian Space Research Organisation (ISRO), Government of India, Bangaluru | VLSI Design |