Executive Summary : | System-on-chip (SoC)-based designs rely on the usage of reusable intellectual property (IP) cores. IP-based design has become a common practice in electronic system design, as it drastically reduces design time, cost, and speed from concept to prototype for fast time to market. SoC cores involve several developers for design, validation, verification, fabrication, testing, etc. Designers also outsource their manufacturing and circuit fabrication to specialized companies around the world. Here, IPs used in SoC designs are subjected to various threats, particularly IP theft or piracy, reverse engineering, malicious modification, IC overbuilding, Trojan attacks, or side-channel attacks (SCAs). Logic locking is an important Design-for-trust (DfTr) technique to protect IPs from unauthorized access and reverse engineering. It can provide post-fabrication programmability by introducing key-programmable logic gates or Key Gates (KGs) regulated by the key bits of the logically locked netlist. The locked design is fully functional and generates the right result with the use of the correct key bits for the correct result. The protected logic used determines the security properties of the logic locked design. Depending on the requirement, algorithms and methodologies will be developed to protect IPs and counter side-channel attacks. AI/ML classification models with graph neural networks (GNNs) will be utilized. However, logic locking is not a fully proofed solution, and attackers can use various attacks to bypass the lock. Therefore, researchers have proposed various defense mechanisms to enhance the security of logic locking. Machine learning is one of the techniques proposed for the defense of logic locks. AI/ML techniques are widely used in electronic system design and security applications. Hardware security problems can be efficiently addressed by incorporating AI/ML techniques. The idea is to use machine learning algorithms to analyze the behavior of the locked circuit and detect any anomalies that could indicate an attack. By using machine learning, the defense mechanism can adapt to new attack patterns and protect the locked circuit from future attacks. The definition of an attack algorithm can be either ML-based attacks such as SAIL, SURF, GNNUnlock, OMLA attack, etc. These techniques are based on oracle-guided or oracle-less algorithms to provide an effective defense against attacks. In this work, ML-guided design-for-security (DfS) methods would be used for data security and logic locking of digital IPs, associated circuits, and systems. The objective will be to define and/or develop IC defense algorithms that protect against antagonistic and unethical use. The proposed work will be carried out on field-programmable gate arrays (FPGA) and CMOS foundry-specific gate-level netlists for application-specific integrated circuit (ASIC) design. Specific deliverables include algorithms, hardware architecture, security circuits, and know-how. |